The invention relates to an integrated memory having global amplifiers which are each assigned a plurality of local amplifiers which serve for amplifying signals present on bit lines of the memory.
Synchronous graphics random access memories (SGRAMs) are special DRAMs (Dynamic RAMs) for graphics applications. Usually, during normal operation, a datum is written to one of the memory cells via one of the global amplifiers and one of the local amplifiers. In this case, the local amplifiers assigned to the same global amplifier are connected thereto via common local data lines. SGRAMs furthermore have a block writing operating mode, in which a datum from a color register is simultaneously written to a plurality of memory cells which, during a normal memory access, are not accessed simultaneously but rather one after the other.
The block writing operating mode serves for writing the same datum from the color register to a plurality of memory cells which are connected to the same word line and are assigned successive column addresses. In this way, a uniform screen color can be generated relatively rapidly for a monitor that is driven by a graphics memory.
Memories of this type are usually constructed in such a way that bit lines which are assigned successive addresses are disposed adjacent to one another. One possibility for carrying out the block writing function consists in simultaneously activating the desired number of local amplifiers connected to the same global amplifier (instead of activating just one of the local amplifiers of the respectively active global amplifier, as in the normal operating mode).
In order to ensure, however, that the global amplifier in the block writing operating mode, can simultaneously supply data for a large number of active local amplifiers, it must be given sufficiently large dimensions, which results in a corresponding large space requirement.
It is accordingly an object of the invention to provide an integrated memory with a block writing function that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which the global amplifiers require less space. With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, including word lines; bit lines intersecting the word lines; memory cells disposed at crossover points of the bit lines and the word lines; local amplifiers connected in each case to at least one of the bit lines; and at least two global amplifiers connected in each case to a plurality of the local amplifiers, in a first operating mode during each write access only one of the two global amplifiers being active and transmitting a datum via one of the local amplifiers to a corresponding one of the bit lines, and in a second operating mode during the write access two of the global amplifiers being simultaneously active and transmitting a common datum via in each case at least one of the local amplifiers to corresponding ones of the bit lines.
The memory according to the invention has a first operating mode, in which, during each write access, only one of the two global amplifiers is simultaneously active and transmits a datum via one of the local amplifiers to the corresponding bit line. Moreover, it has a second operating mode, in which, during each write access, both global amplifiers are simultaneously active and transmit a common datum via in each case at least one of the local amplifiers to the corresponding bit lines.
In the case of the memory according to the invention, more global amplifiers are simultaneously active in the second operating mode, which may be a block writing operating mode for example, than in the first operating mode. Therefore, the common datum is simultaneously written to a plurality of memory cells not by a single active global amplifier but by a plurality of global amplifiers. If the number of memory cells that are to be written to simultaneously is prescribed, and thus so is the number of local amplifiers that are to be activated simultaneously during the block writing operation, in the case of the invention each global amplifier has to drive, simultaneously, significantly fewer active local amplifiers compared with the case where all of the local amplifiers that are to be activated simultaneously would be driven by only one global amplifier. The capacitive loading on the global amplifier rises with the number of active local amplifiers that the global amplifier has to drive simultaneously. Since the invention makes it possible, therefore, to reduce the capacitive loading on the global amplifiers in the block writing operating mode, the global amplifiers can be given correspondingly smaller dimensions. This leads to a reduction in the space requirement of the global amplifiers and hence to an overall decrease in the space requirement of the integrated circuit.
In accordance with an added feature of the invention, there are column select lines transmitting column addresses and connected to the local amplifiers, the bit lines are selected by use of the column addresses, and the bit lines which, in the second operating mode, are accessed simultaneously via the two of the global amplifiers during the write access are assigned successive ones of the column addresses.
In according with an additional feature of the invention, there is a memory unit for storing the datum and connected to the global amplifiers. In addition, a data input is connected to the global amplifiers and, through which, in the first operating mode, the datum to be written in can be fed to the global amplifiers without being stored in the memory unit, and the global amplifiers in the second operating mode, simultaneously transmitting the datum stored in the memory unit through in each case at least one of the local amplifiers to the corresponding bit lines.
In accordance with a concomitant feature of the invention, during the second operating mode and during the write access, all of the global amplifiers transmit the common datum simultaneously through in each case a plurality of the local amplifiers to the corresponding ones of the bit lines.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.